OK, I admit there is no such thing as a “perfect” FPGA module, but one should at least try to come as close as possible. So when we, at Knowledge Resources, contemplated the use of pre-built FPGA modules in order to accelerate the development of some simpler small run projects, we looked at commercially available offerings and found them to be interesting but never quite right for our needs. In addition to imperfect fit, they were also rather expensive, at least when considered in small quantities. So we started our own module design in the spring of 2012. Here are the thoughts that drove the shape and features of our first module family, the KRM1k.:
- It needs to be as universally useable as possible, therefore we were aiming for as many generic I/O’s as possible and tried to avoid special purpose I/O’s such as dedicated USB, ethernet or video.
- It needs to significantly simplify the design of the carrier board. Simplification comes in two forms:
- Fewer layers are required compared to a design that has the FPGA BGA package directly on the main PCB
- The PCB trace & spacing geometries can be relaxed
- It needs to be low cost enough so that it is a viable commercial option for applications ranging from quick projects, educational kits and small to medium volume products.
- Spare FPGA pins that cannot be exposed as module I/O’s (due to the modules pin constraints) may be used to implement “nice to have” features on the module as long as they do not add significant cost to the final module. Examples include logic analyzer test points, (which come for free if implemented for connectorless probes) or status LED’s or maybe a micro SD connector for more local storage…all nice to have and less than 1% impact on the modules BOM.
It turns out that the universal usability is a key feature and a big distinguishing aspect of Knowledge Resources modules from the competitors offerings. In order to being universal, the first design rule is that…
…the modules only carry features that are required in every design.
- Core power supply
- Configuration memory
- Reset and proper initialization
This first rule is broken slightly by adding features that are highly likely to be needed and would…
add significant complexity to the design if they had to be implemented on the carrier.
- DDR memories
- Use of small pitch & high I/O count FPGA packaging
For our first design, we chose the Xilinx Spartan6 LX75 in the GFF676 packaging because it offers the largest Spartan 6 FPGA that is still supported by the free ISE web-pack (we considered that important for hobbyist and educational clients) but offers a reasonably large amount of logic and multiple hard IP memory controllers, has a pin-compatible upgrade path (LX 100 & LX150) and a downgrade path (LX45). The SO-DIMM form factor choice was largely driven by the low cost of the mating connector and the connector-less aspect of the module (also a cost consideration). In hindsight, this was not well considered since the 200 pins available on a SO-DIMM header turn out to be a severe I/O constraint if one designs the module with ample GND and power pins so that even designs that need to bring faster signals into or out of the module, have a chance of functioning properly. Since, even after implementing two separate instances of DDR III Memory, we had so many unused pins on the FPGA, we added two 50 pin Ziff connector expansion ports. Each of the ports expose 32 GP I/O’s, and 2 clock pairs, provide ample GND and 3.3V supply to the expansion module.
The end result is our KRM-1075-512-x, a pretty useful, nearly perfect module that we have used in several projects and countless “quick experiments” . It may not be perfect, but it sure does come close 😉