KR-DDR4 IP is a high-performance memory controller tailored
for use with PL DDR4 memory on AMD/Xilinx UltraScale+
families of SoMs by Knowledge Resources.
KR-DDR4 Memory Controller IP
Description
KR-DDR4 Memory Controller IP
- Full DDR4 memory controller including PHY layer
- Pre-calibrated SoM-specific PHY configuration tested for thermal stability
- Very small footprint:
- more than 4x lower CLB usage compared to AMD/Xilinx MIG DDR4 v2.21
- zero BRAM/DSP usage
- High performance:
- 2400 MT/s
- 89% / 89.8% / 78 % efficiency for sequential Write/Read/Read-Write
- sub-millisecond (< 500 us) core initialization time
- 128- / 256- / 512-bit wide AXI4 data interface2
- 128- / 256- / 384- / 576-bit wide Native data interface3
- ECC support with AXI4-Lite control/status interface4
- Easy to use:
- available as Vivado IP packages (Verilog HDL and pre-synthesized EDF)
- integrated synthesis/implementation constraints
- Vitis Classic/Unified software driver support
1FPGA resource usage for a dual 512-bit DDR4 controller design on KRM-4ZU47DR SoM
2,3,4Depending on the SoM
Variants
| MODULE | Q 1-10 | MOQ |
|---|---|---|
| KR-DDR4 IP | € price upon request | 1 |
Inquire for lead times
MOQ1 also indicates that sample stock is usually available with no lead time.
